Re: [TCLUG:3420] MIPS is dead

[Brad_C_Elkin@notes.seagate.com]

I stand corrected. Comes from being a Mac loyalist, I guess.
Ah well, at least SPARC is still RISC.

Also, I heard MERCED will be a variation on VLIW. Can anyone confirm/deny?
The implication is that it's getting too expensive to get performance by
bumping the
clock rate up..





Michael Hicks <hick0088@tc.umn.edu> on 01/18/99 11:13:05 AM

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To:   tclug-list@listserv.real-time.com
cc:    (bcc: Brad C Elkin)
Subject:  Re: [TCLUG:3420] MIPS is dead




> This economies-of-scale thing is depressing, but inexorable. I
> always considered the PPC architecture (and RISC in general) to be
> technologically superior. I watch with amazement as an inferior
> CISC architecture wins out in the marketplace.

I hate to burst your bubble, but PPC is almost as CISC as Intel..  I'm
not certain about the specifics (I wish I was), but RISC (as defined by
IBM for PPC) doesn't have the traditional meaning.  IBM uses RISC to
stand for Reduced Instruction Set Cycles -- meaning that more work can
get done in a sincle clock tick.  PPC still has quite a large set of
instructions (over 200, I believe) where most traditional RISC systems
have less than 100.

Some more info can be found at
http://www.cs.uregina.ca/~bayko/cpu.html#POWER (be warned, it's quite a
large document -- ~250kB.  All text, though..)

Still, I like PPC.  It's still cleaner than Intel, plus the actual
architecture seems to be more flexible (PPC is based on a specification,
not a chip, IIRC)
--
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|               Mike Hicks | Linux User Since: 1.2.13
: http://umn.edu/~hick0088 | mailto:hick0088@tc.umn.edu
`              icq:6883760 | Current Kernel: 2.2.0-pre6

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